This course covers the VHDL Programming Language from the basic to the intermediate level. We have presented basics of VHDL Language, its syntax/semantics, conditional statements, process statement with example project on Quartus prime tool. We also have Lab session on Combinatorial circuit design, sequential circuit design and state machine design.
This course also have sessions on writing the testbench module and simulating it with Modelsim. Another method of simulation and verification of VHDL design, Vector Waveform Generator is also presented in this course with Example.
Another Important part of this course is "Structural Design Methodology" in VHDL, we showed the design of "Full Adder" using the "Half Adder" module with Structural Design Method.