- Introduction to Course
- Need for Verification Methodologies
- Layered Testbench Architecture - Concepts and Importance
- Download Course Resource And Assignment Instructions
- Introduction to OVM, UVM Concepts
- Transaction Level Modelling Basics
- TLM Interfaces - Ports and Exports, FIFOs
- TLM Interfaces - Analysis Ports and FIFOs
- Test your basics on Transaction Level Modelling
- Assignment 1 : Producer Consumer Example Code Simulation
- Testbench Components and Hierarchy
- Building Driver and Sequencer Components
- Sequencer to Driver Connection
- Building a Monitor Component
- Building an Agent Component
- Environment and Test Class Components
- Building and Connecting Testbench Components
- Understanding Simulation phases
- Test your concepts on Testbench Components
- Basics of Sequence based Stimulus Generation
- Sequence Items and Methods
- Sequences and its Methods
- Sequencer and Driver API
- Sequence Generation Styles
- Basics of Virtual Sequences
- Test your basics on Sequence based Stimulus generation
- Basic Concepts of OVM/UVM Factory
- Testbench Configuration in UVM
- End of Test Mechanisms in UVM
- Assignment Overview
- Introduction to APB Protocol
- APB Testbench Architecture
- Creating APB Transaction and Interface
- Creating APB Driver and Sequencer
- Creating APB Monitor
- Creating APB Agent And Env
- creating Sequences
- Building Test, Top Module and Simulating your test
- Summary