- What's Inside?
- How to Install Vivado 2019.1
- Part 1
- Part 2
- Part 3
What you'll learn
- Creating your first Vivado project
- All basic steps with the detailed explanation
- Vivado Design Suite interface and options
- Fundamental flow from code to program the device
Description
AMD/Xilinx Vivado Design Suite is a toolset designed by Xilinx for the synthesis and analysis of HDL (Verilog\System Verilog or VHDL). It does have its own simulator, router, and IP integrator.
This course covers the fundamentals of the Vivado Design Suite IDE flow that includes
- Creating a simple project (an example design for learning purposes)
- Explanation of the Vivado Design Suite Interface and useful options in details
- Simulating it using the Vivado simulator (behavioral simulation)
- Doing RTL Analysis (viewing the circuit in terms of digital components i.e., adders, multiplexers, registers, etc,.)
- Writing up the constraints (pins locations properties, clocks, etc.,)
- Synthesize the design (exploring netlist)
- Doing place and route (add implementation runs)
- Generating the bitstream (binary file)
- Programming the device using Vivado Hardware Manager
If you are a student and just started learning the Xilinx FPGA chipset this course is for you
- OR -
If you are an FPGA hobbyist who is willing to learn Vivado for fun projects then you are at the right place to begin with
- OR -
Even if you are a working professional who is switching from other toolsets to AMD/Xilinx toolsets then you should be watching this series to make yourself familiar with the tool environment.
Happy Development!
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About the instructors
- 4 Calificación
- 783 Estudiantes
- 1 Cursos
Uzaif Sharif
FPGA Design Engineer
Uzaif is an FPGA Design Engineer. He did his bachelor's in Electronics Engineering and then pursued post-graduation in Electrical Engineering with a concentration in Digital and Computer Engineering. He did lots of academic projects including robotics and FPGAs. As an active member of the MARS (Methodologies and Architectures for Reconfigurable SoCs) group, he was involved in the Research & Development of accelerated real-time implementation of a colored object tracking system using High-Level Synthesis. He has experience in FPGA design and development with HDLs (Verilog/VHDL) and System-on-Chip.
Uzaif is a professional FPGA developer who has been working in the field for 4+ years. He has impressive skills in Digital Circuits, Simulations, Synthesis and P&R, Timing Analysis, CDCs, Design Optimization, Ethernet protocols, etc.
He loves to share his knowledge!
Student feedback
Course Rating
Reviews
Nice One Bro❤️
good course for beginners
Good
Nice presentation. Interesting course. It will help more beginners to start the FPGA design.
not discussed about ip intergator
Wow Great course . Thanks a lot for sharing this knowledge with me.
Great