Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system. Course is all about the history of the Verilog HDL language, an approach to learning Verilog, and a first phrase design example done three different ways showing the versatility of Verilog, the basics of Verilog syntax, Verilog variable values and data types, and some suggested editors that can be used to create Verilog code, how to use the assignment statements and also about the wide range of operators in Verilog and how they work, Verilog data types, what they mean and how to use them, and the difference between Nets and Registers, which are the two main data types found in Verilog, how to use modules as building blocks of Verilog circuit design descriptions, how to include an instance of another module within a module to build hierarchical designs, and two ways to instantiate a module, and which one is better, how to describe combinatorial circuits and Vera log and how to reduce Vector sizes using reduction operators, how to describe synchronous circuits in Verilog, and how to design flip-flops and latches in Verilog, how to describe basic sequence circuits and very log and how to design registers and counters in Barrel log, how to build bigger designs using modular design techniques, the use of loops in Verilog log, and how to use for Generate to make copies of circuits.
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I am Kaithi Nirmalakumari, Assistant Professor at K.K.Wagh Institute of Engineering Education and Research, Nashik, India. I Completed BE in Electronics and Communication Engineering from Osmania University, Hydearabad-India and M.Tech in VLSI Design from Jawaharlal Technological University, Hyderabad-Inida. I have total 15 Years of teaching experience. I am much interested in VLSI Design.
